1. Field of the Invention
The present invention relates generally to microelectronic fabrications. More particularly, the present invention relates to microelectronic fabrications having microelectronic capacitor structures fabricated therein.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
In addition to the fabrication of transistor structures, resistor structures and diode structures within microelectronic fabrications, it is also common in the art of microelectronic fabrication to fabricate capacitor structures within microelectronic fabrications. Capacitor structures within microelectronic fabrications are employed within microelectronic fabrications including but not limited to: (1) data storage and retrieval microelectronic fabrications (such as semiconductor integrated circuit memory microelectronic fabrications); and (2) signal processing microelectronic fabrications (such as semiconductor integrated circuit mixed signal (i.e., integrated digital and analog signal) microelectronic fabrications and semiconductor integrated circuit logic microelectronic fabrications).
While capacitor structures are thus clearly desirable in the art of microelectronic fabrication and often essential in the art of microelectronic fabrication, capacitor structures are nonetheless not entirely without problems in the art of microelectronic fabrication.
In that regard, it is often difficult in the art of microelectronic fabrication to fabricate, with enhanced reliability and performance, microelectronic fabrications having formed therein capacitor structures.
It is thus desirable in the art of microelectronic fabrication to fabricate, with enhanced reliability and performance, microelectronic fabrications having formed therein capacitor structures.
It is towards the foregoing object that the present invention is directed.
Various capacitor structures having desirable properties, and methods for fabrication thereof, have been disclosed in the art of microelectronic fabrication.
Included among the capacitor structures and methods for fabrication thereof, but not limited among the capacitor structures and methods for fabrication thereof, are capacitor structures and methods for fabrication thereof disclosed within: (1) Sun, in U.S. Pat. No. 6,198,617 (a capacitor structure having enhanced performance incident to being formed as a metal-insulator-metal (MIM) capacitor structure with a first metal plate layer formed of an electromigration resistant material); (2) Tsai, in U.S. Pat. No. 6,232,197 (a capacitor structure having enhanced performance incident to being fabricated in part employing a damascene method); (3) Adler et al., in U.S. Pat. No. 6,259,128 (a metal-insulator-metal (MIM) capacitor structure formed with enhanced performance incident to being formed employing multiple barrier layers); and (4) Chen, in U.S. Pat. No. 6,300,682 (a capacitor structure having enhanced performance incident to being formed with a guard ring encircling an upper capacitor electrode plate within the capacitor structure).
Desirable in the art of microelectronic fabrication are additional microelectronic fabrications with enhanced reliability and performance, as fabricated having formed therein capacitor structures.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a microelectronic fabrication having formed therein a capacitor structure and a method for fabricating the microelectronic fabrication having formed therein the capacitor structure.
A second object of the present invention is to provide the microelectronic fabrication and the method for fabricating the microelectronic fabrication in accord with the first object of the present invention, wherein the microelectronic fabrication is fabricated with enhanced reliability and performance.
In accord with the objects of the present invention, there is provided by the present invention a microelectronic fabrication and a method for fabricating the microelectronic fabrication.
To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a first dielectric layer having formed exposed therein a pair of patterned first conductor layers. There is then formed over the first dielectric layer including the pair of patterned first conductor layers a blanket second dielectric layer. There is then patterned the blanket second dielectric layer to form a patterned second dielectric layer which defines a first via which accesses one of the pair of patterned first conductor layers but not the other of the pair of patterned first conductor layers. There is then formed into the first via a first conductor interconnect stud layer. There is then formed contacting the first conductor interconnect stud layer and over the patterned second dielectric layer a capacitor structure. There is then patterned additionally, after having formed the capacitor structure, the patterned second dielectric layer to form a twice patterned second dielectric layer which defines a second via which accesses the other of the pair of patterned first conductor layers. Finally, there is then formed into the second via a second conductor interconnect stud layer.
There is provided by the present invention a microelectronic fabrication having formed therein a capacitor structure and a method for fabricating the microelectronic fabrication having formed therein the capacitor structure, wherein the microelectronic fabrication is fabricated with enhanced reliability and performance.
The present invention realizes the foregoing object by forming the capacitor structure within the microelectronic fabrication upon a conductor interconnect stud layer formed into a first via defined by a patterned second dielectric layer to access one of a pair of patterned first conductor layers formed within a first dielectric layer formed beneath the patterned second dielectric layer, prior to forming through the patterned second dielectric layer a second via to access the other of the pair of patterned first conductor layers.